1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a semiconductor memory device having a self refresh mode.
2. Description of the Background Art
FIG. 10 is a block diagram showing an overall configuration of a conventional dynamic random access memory (hereinafter, referred to as a DRAM). Referring to FIG. 10, the DRAM includes a POR (Power On Reset) circuit 31, a self refresh circuit 32, a clock generation circuit 33, a row/column address buffer 34, a row decoder 35, a column decoder 36, a memory mat 37, a data input buffer 40, and a data output buffer 41. Memory mat 37 has a memory array 38 and a sense amplifier+input/output control circuit 39.
In response to application of an external power supply potential VCC and an external ground potential VSS, POR circuit 31 outputs a signal /POR for resetting the DRAM. In response to external control signals /RAS, /CAS designating execution of refreshing, self refresh circuit 32 increments row address signals RA0 to RAm (m is an integer of at least 0) in a predetermined cycle. Clock generation circuit 33 selects a prescribed operation mode based on external control signals /RAS, /CAS, /WE and thus controls the entire DRAM.
Row/column address buffer 34 generates row address signals RA0 to RAm and column address signals CA0 to CAm according to external address signals A0 to Am, and applies signals RA0 to RAm and CA0 to CAm thus generated to row decoder 35 and column decoder 36, respectively.
Memory array 38 includes a plurality of memory cells each storing 1-bit data. Each memory cell is arranged at a prescribed address determined by row and column addresses.
Row decoder 35 designates row addresses of memory array 38 according to row address signals RA0 to RAm applied from row/column address buffer 34 or self refresh circuit 32. Column decoder 36 designates column addresses of memory array 38 according to column address signals CA0 to CAm applied from row/column address buffer 34.
Sense amplifier+input/output control circuit 39 reads out data of a memory cell at a row address designated by row decoder 35, and connects a memory cell at a column address designated by column decoder 36 to one end of a data input/output line pair IOP. The other end of data input/output line pair IOP is connected to data input buffer 40 and data output buffer 41. In a writing mode, data input buffer 40 applies externally input data D0 to Dn (n is an integer of at least 0) to selected memory cells through data input/output line pair IOP and rewrites data of the memory cells. In a reading mode, data output buffer 41 supplies read data Q0 to Qn as an output from selected memory cells in response to an external control signal /OE.
FIG. 11 is a circuit diagram showing a configuration of DRAM memory mat 37 shown in FIG. 10. Here, only a portion corresponding to 1/bit data DQ0 is shown.
In FIG. 11, memory array 38 includes a plurality of memory cells MCs arranged in rows and columns, a word line WL provided for each row, and a pair of bit lines BL, /BL provided for each column. Each memory cell MC includes an N channel MOS transistor for accessing and a capacitor for storing information as is well known. One end of word line WL is connected to row decoder 35.
Sense amplifier+input/output control circuit 39 includes a column selection line CLS, a column selection gate 42, a sense amplifier 43 and an equalizer 44 which are provided for each column. Column selection gate 42 includes two N channel MOS transistors connected between bit lines BL, /BL and data input/output lines IO, /IO, respectively. The two N channel MOS transistors have their gates connected to column decoder 36 through column selection line CSL. When column selection line CSL is raised to a logical high or H level selected state by column decoders 36, the two N channel MOS transistors are rendered conductive and thereby the pair of bit lines BL, /BL and the pair of data input/output lines IO, /IO are connected.
Sense amplifier 43 amplifies a small potential difference between the pair of bit lines BL, /BL to a power supply voltage VCC in response to sense amplifier activation signals SON, ZSOP attaining logical high and low or H and L levels, respectively. Equalizer 44 equalizes the potentials of bit lines BL, /BL to a bit line potential VBL in response to a bit line equalize signal BLEQ attaining an H level active state.
In the following, an operation of the DRAM shown in FIGS. 10 and 11 will be described. In the writing mode, column selection line CSL in a line corresponding to column address signal CA0 to CAm is raised to the H level selected state by column decoder 36, and column selection gate 42 in the column is rendered conductive.
In response to signal /WE, data input buffer 40 applies externally applied write data to a bit line pair BL, /BL in the selected column through data input/output line pair IO, /IO. The write data is applied as a potential difference between bit lines BL, /BL. Then, word line WL in a row corresponding to row address signal RA0 to RAm is raised to an H level selected state by row decoder 35, and N channel MOS transistors of memory cells MCs in that row are rendered conductive. Electric charges of such an amount that corresponds to the potential of bit line BL or /BL are stored in the capacitor of a selected memory cell MC.
In the reading mode, bit line equalize signal BLEQ is first lowered to an L level to stop equalization of bit lines BL, /BL, and word line WL in a row corresponding to row address signal RA0 to RAm is raised to an H level selected state by row decoder 35. The potentials of bit lines BL, /BL are slightly changed according to the amount of electric charges in the capacitor of activated memory cell MC.
Then, sense amplifier activation signals SON, ZSOP are driven to H and L levels, respectively, thus activating sense amplifier 43. When the potential of bit line BL is slightly higher than the potential of bit line /BL, the potential of bit line BL is raised to an H level and the potential of bit line /BL is lowered to an L level. Conversely, when the potential of bit line /BL is slightly higher than the potential of bit line BL, the potential of bit lines /BL is raised to an H level and the potential of bit line BL is lowered to an L level.
Then, column selection line CSL in a column corresponding to column address signal CA0 to CAm is raised to the H level selected state by column decoder 36 and thereby column selection gate 42 in the column is rendered conductive. Data of bit line pair BL, /BL in the selected column is applied to data output buffer 41 through column selection gate 42 and data input/output line pair IO, /IO. Data output buffer 41 supplies the read data as an output in response to signal /OE.
In a self refresh mode, row address signal RA0 to RAm generated by self refresh circuit 32 is applied to row decoder 35 instead of row address signal RA0 to RAm from row/column address buffer 34. Row decoder 35 drives one word line WL of a plurality of word lines WL in memory array 38 to an H level selected state according to row address signal RA0 to RAm from self refresh circuit 32. Similarly to the reading mode, sense amplifier 43 and equalizer 44 are driven in synchronization with row decoder 35, and data once read out from each memory cell MC to bit line pair BL, /BL is written to memory cell MC again. Row address signal RA0 to RAm from self refresh circuit 32 is incremented in a prescribed cycle. Therefore, until a designation to stop self refreshing is issued, data in memory cells MCs in a plurality of rows included in memory array 38 is sequentially refreshed for each row.
FIG. 12 is a block diagram showing a configuration of self refresh circuit 32. In FIG. 12, self refresh circuit 32 includes a CBR determination circuit 51, a basic cycle generation circuit 52, an REFS generation circuit 53, an internal RAS generation circuit 54, and an internal address generation circuit 55. CBR determination circuit 51 raises an internal control signal CBR to an H level active state in response to reception of signals /CAS, /RAS at timing of CBR (/CAS before /RAS), that is, in response to signal /RAS falling to an L level active state after signal /CAS falls to an L level active state. Basic cycle generation circuit 52 is activated in response to the rise of signal CBR to the H level active state, and thereby outputs a clock signal PHYS and its complementary clock signal /PHYS having a constant cycle.
As shown in FIG. 13, REFS generation circuit 53 includes multiple stages (five stages in FIG. 13) of serially connected frequency dividers 61 to 65, five fuses 71 to 75 provided correspondingly to frequency dividers 61 to 65, and a pulse generator 76.
Frequency dividers 61 to 65 are reset by signals ST, RST, and they respectively output clock signals TN1, /TN1; . . . ; TN5, /TN5 each having a cycle twice as high as input clock signals PHYS, /PHYS; TN1, /TN1; . . . TN4, /TN4.
For example, frequency divider 65 at the last stage includes inverters 81, 82, N channel MOS transistors 83 to 92 and capacitance 93, 94 as shown in FIG. 14. Inverter 81 is connected between nodes N81 and N82, and inverter 82 is connected between nodes N82 and N81. Inverters 81 and 82 form a latch circuit. N channel MOS transistors 83, 84 are connected between a ground potential VSS line and nodes N81, N82, respectively, and have their gates receiving signals ST, RST, respectively. Signals appearing at nodes N81, N82 serve as output clock signals /TN5, TN5.
N channel MOS transistor 85 and capacitor 93 as well as N channel MOS transistor 86 and capacitor 94 are connected in series between nodes N81, N82 and the ground potential VSS line, respectively. The gates of N channel MOS transistors 85, 86 both receive output clock signals /TN4 of frequency divider 64 at the previous stage.
N channel MOS transistors 87, 89 as well as N channel MOS transistors 88, 90 are connected in series between nodes N81, N82 and the ground potential VSS line, respectively. The gates of N channel MOS transistors 87, 88 both receive clock signal TN4. The gates of N channel MOS transistors 89, 90 are connected to nodes N85, N86 between N channel MOS transistors 85, 86 and capacitors 93, 94. N channel MOS transistors 91, 92 are connected between nodes N85, N86 and the ground potential VSS line, respectively, and have their gates both connected to the ground potential VSS line. N channel MOS transistors 91, 92 are provided to release a surge current flowing in nodes N85, N86.
In the following, an operation of frequency divider 65 will be described. First, signals RST, ST are set to H and L levels, respectively, and signals TN4, TN5 are reset to an L level. Since signals /TN4 is at an H level at this time, N channel MOS transistors 85, 86 are rendered conductive and thereby nodes N85, N86 are driven to H and L levels, respectively. Furthermore, N channel MOS transistor 89 is rendered conductive, driving its drain (node N87) to an L level, and N channel MOS transistor 90 is rendered non-conductive, driving its drain (node N88) to a floating state.
When signal TN4 rises to the H level, N channel MOS transistors 87, 88 are rendered conductive and N channel MOS transistors 85, 86 are rendered non-conductive, and thus nodes N81, 82, that is, signals /TN5, TN5 are driven to L and H levels, respectively.
When signal TN4 falls to the L level thereafter, N channel MOS transistors 87, 88 are rendered non-conductive and N channel MOS transistors 85, 86 are rendered conductive, and thus nodes N85, N86 are driven to L and H levels, respectively. N channel MOS transistor 89 is rendered non-conductive, driving node N87 to a floating state while N channel MOS transistor 90 is rendered conductive, driving node N88 to an L level. At this time, the levels of signals TN5, /TN5 remain to be at the H and L levels, respectively.
When signal TN4 rises to the H level thereafter, N channel MOS transistors 87, 88 are rendered conductive and N channel MOS transistors 85, 86 are rendered non-conductive, and thus nodes N81, N82, that is, signals /TN5, TN5 are driven to H and L levels, respectively. Therefore, frequency divider 65 generates clock signals TN5, /TN5 each having its frequency twice as high as input clock signals TN4, /TN4. Other frequency dividers 61 to 64 have the same structure as frequency divider 65.
Referring back to FIG. 13, clock signals /TN1 to /TN5 generated by frequency dividers 61 to 65 are each applied to one electrode of a corresponding fuse 71 to 75. The other electrode of fuse 71 to 75 is connected to an input node 76a of pulse generator 76.
As shown in FIG. 15, pulse generator 76 includes a delay circuit 96 having odd-number stages (three stages in FIG. 15) of serially connected inverters 95, and an OR gate 97. Input node 76a is connected to one input node of OR gate 97 through delay circuit 96 and is also directly connected to the other input node of OR gate 97. An output signal from OR gate 97 serves as signal REFS.
When input node 76a is at an H level, the output signal of delay circuit 96 and signal REFS are at L and H levels, respectively. When input node 76a is driven to an L level, signal REFS falls to an L level. After a delay period of delay circuit 96, the output signal of delay circuit 96 attains an H level and signal REFS rises to the H level. Therefore, pulse generator 76 outputs a negative pulse of a prescribed pulse width in response to a fall of the input signal.
FIG. 16 is a timing chart showing an operation of REFS generation circuit 53 shown in FIGS. 13 to 15. Frequency dividers 61 to 65 output clock signals TN1, /TN1; . . . ; TN5, /TN5 each having its frequency twice as high as input clock signals PHYS, /PHYS; TN1, /TN1; . . . ; TN4, /TN4.
In a wafer state, a self refresh cycle is determined according to the performance of refreshing. Fuses (71 to 73, 75 in this case) other than the fuse (74, for example) to be refreshed are blown. Thus, only selected clock signal /TN4 of clock signals /TN1 to /TN5 is input to pulse generator 76 through fuse 74. Output signal REFS of pulse generator 76 assumes the L level for a prescribed pulse width in response to a falling edge of clock signal /TN4.
Referring back to FIG. 12, internal RAS generation circuit 54 generates signals /RASS, /RAS' in response to signal REFS. Signal /RASS assumes an L level for a prescribed pulse width in response to a rising edge of signal REFS as shown in FIG. 17. Signals /RAS' rises to an H level in response to a falling edge of signal REFS, and falls to an L level for a prescribed pulse width in response to a rising edge of signal REFS. It is noted that the pulse width of signal REFS is a cycle 1/2 times those of clock signals PHYS, /PHYS.
Referring back to FIG. 12, internal address generation circuit 55 is a (m+1)-bit counter, is activated in response to signal CBR attaining an H level active state, counts the pulse number of signal /RASS, and outputs row address signals RA0 to RAm. Therefore, row address signals RA0 to RAm are implemented each time signal /RASS falls to the L level. In the self refresh mode, instead of row address signals RA0 to RAm from row/column address buffer 34, row address signals RA0 to RAm generated by internal address generation circuit 55 are applied to row decoder 35.
Since conventional DRAMs are formed as described above, the self refresh cycle cannot be changed once it is set in a wafer state. Therefore, if the refresh performance is deteriorated by process variation after setting the self refresh cycle, the DRAM causes a refresh failure and becomes a defect.